For implementing CAM, DRAM offers compelling advantages over static random access memory (SRAM). DRAM is smaller in size than SRAM. Thus, on a given area, DRAM offers inherently a denser memory than what SRAM can offer. As such, more information can be stored using DRAM. Also, because the more integration on a chip the better the performance, DRAM improves performance. Moreover, DRAM inherently consumes less power than SRAM, making DRAM well suited for high density CAM, wherein power consumption is a critical issue. Further still, DRAM requires fewer transistors per cell when compared to SRAM. Thus, DRAM lowers manufacturing cost. In summary, compared to SRAM, DRAM offers higher density, higher performance, lower power consumption, and lower manufacturing cost.
However, DRAM necessitates refresh overhead that slows the speed performance of CAM. This speed penalty defeats the purpose of using CAM, which is to provide high-speed memory access. In fact, CAM is required precisely in time critical applications. Nevertheless, because of the very nature of DRAM, refresh cannot be avoided. The voltage leakage of the capacitors in DRAM cells demands that refresh be performed to preserve stored data.
Thus an impasse has been reached, wherein on the one hand DRAM-based CAM offers many distinct advantages compelling benefits over SRAM-based CAM, and wherein on the other hand speed penalty of DRAM-based CAM defeats the purpose of using a CAM for time critical applications. In view of this impasse, a need exists for taking advantages of DRAM in implementing CAM while not paying the speed penalty caused by DRAM refresh.